Deployment

Create bitstream containing user programming and download it to Intel^®SoC platform

HDL Coder™ can generate an IP core, integrate it into your Qsys project, and program the Intel hardware. Using Embedded Coder^®, you can generate and build the embedded software, and run it on the ARM^®processor.

Topics

Default System Reference Design
设计一个学习系统默认引用d using the reference design.
Default System with External DDR4 Memory Access Reference Design
Learn about the default system with external DDR3 memory access reference design and its requirements.
Simulink Hardware-Software Co-Design for Intel SoC Platform
Hardware-software co-design workflow example for Intel SoC Platform.

Related Information

Intel SoC Devices

Featured Examples

Perform Matrix Operation Using External Memory

Generate an HDL IP core with AXI4 Master interface, perform matrix multiplication in HDL IP core, and write output result to DDR memory.