Actual code generation support depends on block implementation.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic. For information about best practices, restrictions, and how you can use the trigger signal as a clock with theTriggerAsClockproperty, seeUsing Triggered Subsystems for HDL Code Generation(HDL Coder).
HDL Architecture
| Architecture |
Description |
Module(default) |
Generate code for the subsystem and the blocks within the subsystem. |
BlackBox |
Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals. |
No HDL
|
Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code. |
HDL Block Properties
| General |
| AdaptivePipelining |
Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default isinherit. See alsoAdaptivePipelining(HDL Coder). |
| BalanceDelays |
Detects introduction of new delays along one path and inserts matching delays on the other paths. The default isinherit. See alsoBalanceDelays(HDL Coder). |
| ClockRatePipelining |
Insert pipeline registers at a faster clock rate instead of the slower data rate. The default isinherit. See alsoClockRatePipelining(HDL Coder). |
| ConstrainedOutputPipeline |
Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is0. For more details, seeConstrainedOutputPipeline(HDL Coder). |
| DistributedPipelining |
Pipeline register distribution, or register retiming. The default isoff. See alsoDistributedPipelining(HDL Coder). |
| DSPStyle |
Synthesis attributes for multiplier mapping. The default isnone. See alsoDSPStyle(HDL Coder). |
| FlattenHierarchy |
Remove subsystem hierarchy from generated HDL code. The default isinherit. See alsoFlattenHierarchy(HDL Coder). |
| InputPipeline |
Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, seeInputPipeline(HDL Coder). |
| OutputPipeline |
Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is0. For more details, seeOutputPipeline(HDL Coder). |
| SharingFactor |
Number of functionally equivalent resources to map to a single shared resource. The default is 0. See alsoResource Sharing(HDL Coder). |
| StreamingFactor |
Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See alsoStreaming(HDL Coder). |
Target Specification
This block cannot be the DUT, so the block property settings in theTarget Specificationtab are ignored.
Restrictions
HDL code generation supports only boolean datatype at the trigger input.
Actual data type support depends on block implementation.
