Curie 's pick of the week is - later, make that plural!My picks are theHDL Coder TutorialThe andHDL Coder Evaluation Reference Guide, both byJack Erickson.

If you weren 't aware, you can generate HDL (hardware description language) code from MATLAB and金宝app Simulink to program the custom FPGA or ASIC hardware. I have worked with customers that are targeting an FPGA for the first time, to customers with decades of ASIC design experience who want to connect their chip design workflow to model - -based design to improve their agility and efficiency.

A powerful tool to the asHDL CoderMeans there is a learning curve, especially if you are new to 金宝appSimulink. To help you get started, the tutorial provides a step - by - step instructions on how to take this sample MATLAB code:

% Correlate Rx filter against matched filterFilterOut = filter (CorrFilter, 1, RxSignal);% the Find peak magnitude and the location[peak, the location] = Max (abs (FilterOut));

To a 金宝appSimulink architectural, fixed - point model that is ready To generate VHDL or Verilog:

It is as much about learning the Model - -based Design tools as understanding the process of targeting algorithm designs on the FPGA/ASIC hardware.

So you are feeling empowered to start your next HDL design in 金宝appSimulink after completing the tutorial, But you still have So many questions: "What are the best practices to create efficient hardware?""How do I direct the tool to use the FPGA resources to the as RAM and DSP blocks?""I can 't figure out how to model my clock signal!"(You don 't).

The answers to these questions, and many other popular switchable viewer among our users are captured in TheHDL Coder Evaluation Reference Guide28 - page. The document describes design patterns and Settings that produce efficient HDL code, and highlights useful tools that help speed up your design process.

For instance, you will learn how to make local enable signal concerns synchronously;The view timing diagram with the Logic Analyzer scope;And incorporate the MATLAB code in y金宝appour Simulink design using the MATLAB function block - very handy when it comes to the control logic.

And yes, there is an - section devoted to the FPGA resource mapping, with examples to the as this complex multiplier that maps to DSP blocks on Xilinx ® And Intel ® FPGAs:

So don 't let the number of pages scare you and start reading!(Really, half of them are pictures). And if you want to evaluate "capabilities specific to HDL design, my colleagues And I look forward to working with you.

It a boost by the and let us know what you thinkhere!

Get the MATLAB code

Published with MATLAB ® R2019a