Functional Requirements Testing

Generate test cases for functional design requirements

Blocks

Blocks used in Test Case Generation

Test Condition	Constrain signal values in test cases
Test Objective	Define custom objectives that signals must satisfy in test cases
Detector	Detect true duration on input and construct output true duration based on output type
Extender	Extend true duration of input
Implies	Specify condition that produces a certain response
Within Implies	Verify response occurs within desired duration
Verification Subsystem	Specify proof or test objectives without impacting simulation results or generated code

Functions

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Functions used in Test Case Generation

`sldvoptions`	Create design verification options object
`sldv.condition`	Test condition function forStateflowcharts andMATLABFunction blocks
`sldv.test`	Test objective function forStateflowcharts andMATLABFunction blocks
`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvtimer`	Identify, change, and display timer optimizations
`sldvoptions`	Create design verification options object
`sldvrun`	Analyze model
`sldvlogsignals`	Log simulation input port values
`sldvgencov`	Analyze models to obtain missing model coverage
`sldvruntest`	Simulate model by using input data
`sldvruntestopts`	Generate simulation or execution options for`sldvruntest`or`sldvruncgvtest`
`sldvharnessopts`	Default options for`sldvmakeharness`
`sldvmakeharness`	Generate harness model
`sldvmergeharness`	Merge test cases and initializations into one harness model
`sldvreport`	Generate金宝appDesign Verifierreport
`sldvchecksum`	Returns checksum of model

Topics

Introduction to Test Case Generation

What Is Test Case Generation?
Brief overview of test case generation with金宝app^®Design Verifier™.
Workflow for Test Case Generation
Outlines a process for generating test cases for your model.
Use Test Generation Advisor to Identify Analyzable Components
Use the Test Generation Advisor to guide model and component analysis.
Configuring S-Function for Test Case Generation
This example shows how to compile an S-Function to be compatible with Simulink® Design Verifier™ for test case generation.
Generate Test Cases for Embedded Coder Generated Code
Outlines a process for generating test cases for generated code.
Code Coverage Test Generation
This example shows how to use Simulink® Design Verifier™ to generate test cases to obtain complete code coverage.
Export Test Cases to Simulink Test
Describes how to generate test cases inSimulink Test™usingSimulink Design Verifieranalysis results, which can be generated by property proving, design error detection, and test case generation.
What is a Specification Model?
Overview of specification model and its use in requirements-based verification.

Component Verification

What Is Component Verification?
An overview of the two approaches to component verification.
Functions for Component Verification
Describes theSimulink Design Verifierfunctions you can use for component verification.
Verify a Component for Code Generation
This example uses theslvnvdemo_powerwindowmodel to show how to verify a component in the context of the model that contains that component.
Isolate Verification Logic with Observers
Describes the observer support for simulink design verifier.

Parameter Configuration

Parameter Configuration for Analysis
Overview of parameter configuration forSimulink Design Verifieranalysis.
Specify Parameter Configuration for Full Coverage
An example of how to specify parameter constraint values to achieve full model coverage.
Specify Parameter Configuration for Structure or Bus Parameters
This example describes how to generate tests that constrain the values for the structures and bus signals in a model.

Simulink Design Verifier Pane

Design Verifier Pane: Test Generation
Specify options that control howSimulink Design Verifiergenerates tests for the models it analyzes.
Design Verifier Pane: Parameters and Variants
Specify options that control howSimulink Design Verifieruses parameter configurations when analyzing models.
Design Verifier Pane
Specify analysis options and configureSimulink Design Verifieroutput.
Simulink Design Verifier Options
Overview of theSimulink Design Verifieroptions in the Configuration Parameters dialog box.
Review Analysis Results
Review analysis results in theSimulink Design VerifierResults Summary window.

Featured Examples

Test Condition Block

限制输入values. The Test Condition block forces the input value to be either 0 or 1.

Open Example

Test Objective Block

The use of two custom Test Objective blocks. The block "True" forces the output signal to be 2. The block "Edge" inside "Masked Objective" specifies that the output signal transition from 2 to 1.

Open Example

Use a Specification Model for Requirements-Based Testing

Use a specification model to perform requirements-based testing. In this example, you follow a systematic approach to verify your design model against requirements. For a detailed description of specification model, see What is a Specification Model?.

Open Script

Generate Test Cases for Model Blocks

Generate Test Cases for Model Reference blocks.

Open Script

Use Observer Reference Block for Test Case Generation

Generate test Cases using Observer Reference blocks.

Open Script