Direct Form

By default, the block implements linear adder logic. When you enableAddPipielineGisters，加法逻辑是作为管道加法树实现的。加法树使用完整的数据类型。如果生成验证模型，则必须在原始模型中使用完全的精度来避免验证不匹配。

转置

TheAddPipielineGisters参数对转置过滤器实现没有影响。

完全连续

A fully serial architecture conserves area by reusing multiplier and adder resources sequentially. For example, a four-tap filter design uses a single multiplier and adder, executing a multiply-accumulate operation once for each tap. The multiply-accumulate section of the design runs at four times the filter's input/output sample rate. This design saves area at the cost of some speed loss and higher power consumption.

In a fully serial architecture, the system clock runs at a much higher rate than the sample rate of the filter. Thus, for a given filter design, the maximum speed achievable by a fully serial architecture is less than that of a parallel architecture.

部分序列

Partly serial architectures cover the full range of speed vs. area tradeoffs that lie between fully parallel and fully serial architectures.

In a partly serial architecture, the filter taps are grouped into a number of serial partitions. The taps within each partition execute serially, but the partitions execute in parallel with respect to one another. The outputs of the partitions are summed at the final output.

When you select a partly serial architecture, you specify the number of partitions and the length (number of taps) of each partition. Suppose you specify a four-tap filter with two partitions, each having two taps. The system clock runs at twice the filter's sample rate.

级联系列

级联式体系结构非常类似于部分串行架构。与部分串行体系结构一样，将滤波器抽头分组为许多串行分区，这些分区相对于彼此并行执行。但是，每个分区的累积输出都级联到上一个分区的累加器。因此，所有分区的输出均在第一个分区的累加器上计算。该技术称为累加器重复使用。不需要最终的加法器，哪个节省区域。

级联式体系结构需要额外的系统时钟周期，以完成对输出的最终求和。因此，必须相对于非cascade部分串行架构中的时钟稍微增加系统时钟的频率。

要生成级联式体系结构，请指定启用累加器重复使用的部分串行体系结构。如果未指定串行分区，则HDL编码器会自动选择最佳分区。

Latency in Serial Architectures

序列化的filter increases the total latency of the design by one clock cycle. The serial architectures use an accumulator (an adder with a register) to add the products sequentially. An additional final register is used to store the summed result of all the serial partitions, requiring an extra clock cycle for the operation. To model this latency, HDL Coder inserts a Delay block into the generated model after the filter block.

完整的连续体系结构

当您选择串行体系结构时，代码生成器在HDL代码中使用完整的精度。因此，HDL编码器在生成的模型中迫使完整的精度。如果生成验证模型，则必须在原始模型中使用完全的精度来避免验证不匹配。