Model Design and Software Interface

Model algorithm to map DUT ports to AXI interfaces and generate software interface to probe and rapidly prototype HDL IP core

When you partition your design into hardware and software components, use the HDL Coder™ HDL Workflow Advisor to target your design on standalone FPGA boards, SoC devices, and Speedgoat^®FPGA IO modules. The design consists of the DUT algorithm for which you generate the RTL code and IP core. You can integrate the IP core into a reference design for the target platform. To test the HDL IP core functionality, you can use a generated software interface model or a software interface script.

Classes

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Board and Workflow

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Target Connection

`fpga`	Access target FPGA or SoC device fromMATLAB
`hdlcoder.DUTPort`	DUT port from anHDL Codergenerated IP core, saved as an object array

Functions

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Reference Design Interfaces

`addAXI4MasterInterface`	添加和定义AXI4主界面
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface

Target Connection Interfaces

`addAXI4SlaveInterface`	Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
`addAXI4StreamInterface`	Write data to IP core or read data from IP core using AXI4-Stream interface
`mapPort`	Maps a DUT port to specified AXI4 interface in HDL IP core
`writePort`	Write data to a DUT port from MATLAB
`readPort`	Reads output data and returns it with the port data type and dimension
`release`	Release the hardware resources associated with the fpga object

Topics

Modeling for AXI Interfaces

Model Design for AXI4 Slave Interface Generation

How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.

Model Design for AXI4-Stream Interface Generation

How to design your model for AXI4-Stream vector or scalar interface generation.

Model Design for AXI4-Stream Video Interface Generation

How to design your model for IP core generation with AXI4-stream video interfaces.

Model Design for AXI4 Master Interface Generation

Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.

Software Interface Generation

Generate Software Interface Script to Probe and Rapidly Prototype HDL IP Core

Generate software interface script to communicate with the HDL IP core and perform rapid prototyping.

Generate Software Interface Model to Probe and Rapidly Prototype HDL IP Core

Generate software interface model to communicate with the HDL IP core and perform rapid prototyping.

Create Software Interface Script to Control and Rapidly Prototype HDL IP Core

Create and author a software interface script by configuring interfaces and port mapping information to control HDL IP core.

Featured Examples

Getting Started with Targeting Intel SoC Devices

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Arrow® SoCKit® evaluation kit.

Open Script

开始使用在Zynq AXI4-Stream接口Workflow

Use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware.

Open Script

Getting Started with AXI4-Stream Video Interface in Zynq Workflow

Use the AXI4-Stream Video interface to enable high speed video streaming on the generated HDL IP core.

Open Script

Performing Large Matrix Operation on FPGA using External Memory

Generate an HDL IP core with AXI4 Master interface, perform matrix multiplication in HDL IP core, and write output result to DDR memory.

Open Script

Prototype FPGA Design on Hardware with Live Data by Using MATLAB Commands

Use MATLAB to prototype an algorithm running on FPGA hardware from your host computer.

Open Live Script

Enable Readback on AXI4 Slave Input Registers to Inspect Written Values

Describes the different techniques to read the AXI4 slave input registers in your design. It shows the process of how to enable readback on AXI4 slave input registers and read the values of AXI4 slave input registers for your design.

Open Script