多相过滤银行

Polyphase filter bank is a widely used technique to reduce inaccuracy in FFT due to leakage and scalloping losses. Polyphase filter bank produces a flatter response as compared to a normal DFT by suppressing out-of-band signals significantly.

The model is a Polyphase Filter Bank which consists of a filter and an FFT that processes 16 samples at a time. For more information about the polyphase filter bank see用于FPGA的高吞吐量通道器（HDL编码器）。

modelname =.'hdlcoder_dpic_testbench';Open_System（ModelName）;

设置模型

The InitFcn callback(Model Properties > Callbacks > InitFcn) sets up the model. In this example, a 512-point FFT with a four tap filter for each band is used. The dsp.Channelizer object is used to generate the coefficients.

The algorithm requires 512 filters (one filter for each band). For a vector input of 16 samples the filter implementation shares 16 filters, 32 times. The input data consists of two sine waves, 200KHz and 250 KHz.

生成HDL代码，HDL测试台和SystemVerilog DPI测试台

Use a temporary directory for the generated files:

WorkingDir = TempName;

检查PolyphaseFilterbank子系统以获取HDL代码生成兼容性：

checkhdl('hdlcoder_dpic_testbench / polyphasefilterbank'那'targetdirectory'，练习犯）;

Run the following command to generate HDL code:

makehdl（'hdlcoder_dpic_testbench / polyphasefilterbank'那'targetdirectory'，练习犯）;

运行以下命令以生成测试台：

makehdltb('hdlcoder_dpic_testbench / polyphasefilterbank'那'targetdirectory'，练习犯）;

这将通过在Simulink中模拟模型然后捕获测试台数据来生成HDL测试台。金宝app

运行以下命令以生成SystemVerilog DPI测试台：

hdlsimulator ='modelsim';％支金宝app持的模拟器选项='modelsim'，'Incisive'，'VCS'，'Vivado'

makehdltb('hdlcoder_dpic_testbench / polyphasefilterbank'那'targetdirectory'，练习呢，'生成vdpitestbench'那HDLSimulator,'generatehdltestbench'那'off'）;

This command generates a SystemVerilog test bench without running a Simulink simulation. Instead of a simulation, the code exports the Simulink system as generated C code inside a SystemVerilog component. The test bench verifies the output data by comparing it with the output of the HDL design. The makehdltb function also generates simulator-specific scripts for compilation and simulation.

SystemVerilog DPI test bench can be used to verify HDL designs of both target languages - VHDL and Verilog.

Alternatively, you can set SystemVerilog DPI test bench options on the 'HDL Code Generation > Test Bench' pane in Configuration Parameters.

生成SystemVerilog DPITest Bench Artifacts

When you request a SystemVerilog DPI test bench, the coder generates the following artifacts:

一个。）polyphasefilterbank_dpi_tb.sv - 这是验证HDL代码的SystemVerilog测试台。

湾）polyphasefilterbank_dpi_tb.do - 这是Mentor GraphicsModelsIm®用于编译HDL代码并运行测试台仿真的宏文件。

基于所选模拟器，编码器生成不同文件以进行编译和测试台型模拟。例如，如果选择“InciSive”，则编码器为CadenceIncisive®的编译和仿真生成“PolyphaseFilterBank_DPI_TB.SH”。

(Optional) Generate HDL Code Coverage Report and Database

借助HDL模拟器以生成HDL代码覆盖报告和数据库，您可以：

a。）在'HDL代码生成>测试台'窗格中，选中标有“HDL代码覆盖范围”的复选框。

湾）当您调用'makehdltb'时，将“hdlcodecoverage”设置为“开”。例如：

makehdltb('hdlcoder_dpic_testbench / polyphasefilterbank'那'targetdirectory'，练习呢，'生成vdpitestbench'那HDLSimulator,'generatehdltestbench'那'off'那'hdlcodecodage'那'上'）;

在模拟测试台后，在源目录中生成HDL代码覆盖伪影。

HDL测试台和SystemVerilog DPI测试台的生成时间比较

The simulation time of the model is set in the pre-load callback (Model Properties > Callbacks > PreLoadFcn)

SIMTIME = 1000;

The sampling frequency is 2e+6 Hz, which means that the simulation to generate the HDL testbench collects 2e+9 samples.

For certain applications, it takes more samples to obtain the right frequency from the polyphase filter. An increase in required simTime would also increase the time required to generate an HDL test bench.

A solution for such applications is to use the SystemVerilog DPI test bench. The generation time for the test bench remains the same no matter how many samples your test scenario requires.

您可以通过更改“SIMTIME”变量来增加模拟时间。例如，为2E + 12个样本生成HDL测试台，设置：

simTime = 1000000;

The table shows a comparison of time taken (in seconds) for generation of HDL test bench and SystemVerilog DPI test bench for increasing numbers of samples (from 2e+9 to 2e+15) :

columns = {'numberofsamples';'GenerateTimehdltestBench';'GenerationTimeSystemVerilogDPITestbench'}; numSamples = [2e9;2e10;2e11;2e12;2e13;2e14;2e15]; HDLTBtime= [10;12;59;504;4994;52200;505506]; DPICTBtime=[47;47;47;47;47;47;47]; CompareTestBenchTimes = table(numSamples,HDLTBtime,DPICTBtime,'variablenames'那columns); disp(CompareTestBenchTimes);

NumberOfSamples GenerationTimeHDLTestBench背包ionTimeSystemVerilogDPITestbench _______________ __________________________ _______________________________________ 2e+09 10 47 2e+10 12 47 2e+11 59 47 2e+12 504 47 2e+13 4994 47 2e+14 52200 47 2e+15 5.0551e+05 47

两种测试时间对于样本数量的生成时间的日志图，表明，虽然HDL测试台需要更多的生成时间随着样本的数量的增加，但是无论的系统verog DPI测试台的生成时间都保持恒定样本数量。

loglog(numSamples,HDLTBtime,'b-o'，numsamples，dpictbtime，'r-o'）;XLIM（[2E09 2E15]）;传说（'HDL测试台'那'SystemVerilog DPI测试台'那'Location'那'西北'）;Xlabel（'样本数量'）;ylabel（'生成时间（以秒为单位）'）;close_system（modelname，0）;

Conclusion

虽然HDL测试台对少量样本非常有效，但如果您的测试场景需要大量样本，则HDL Verifer™SystemVeriLog DPI测试台提供更快的测试台生成。