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Half-Bridge Driver

Behavioral model of half-bridge driver integrated circuit

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  • Simscape / Electrical / Semiconductors & Converters

  • Half-Bridge Driver block

Description

TheHalf-Bridge Driverblock provides an abstracted representation of an integrated circuit for driving MOSFET and IGBT half-bridges. The block models input hysteresis, propagation delay, and turn-on/turn-off dynamics. Unless modeling a gate driver circuit explicitly, always use this block or theGate Driverblock to set gate-source voltage on a MOSFET block or gate-emitter voltage on an IGBT block. Do not connect a controlled voltage source directly to a semiconductor gate, because this omits the gate driver output impedance that determines switching dynamics.

You can model electrical or physical signal input ports by setting theModeling optionparameter to either:

  • PS input— The driver output state is controlled by a physical signal input u. Use this modeling option if all of your controller, including PWM waveform generation, is determined by Simulink®blocks. This modeling option is the default.

  • Electrical input ports— The driver output state is controlled by two electrical input connections, PWM and REF. Use this option if your model has upstream analog components, such as theControlled PWM Voltagesource.

The first pair of output electrical ports, HO and HS, behave in the same way as the G and S ports of theGate Driverblock. Connect these ports to the high-side MOSFET or IGBT of the half-bridge. The second pair of ports, LO and LS, connect to the low-side MOSFET or IGBT of the half-bridge. They behave in a similar way, except that their logic is inverted with respect to that of the high side.

The diagram shows the timing properties for the half-bridge driver, where:

  • tpLHis low-side propagation delay when the input logic goes from 0 to 1.

  • tdLHis high-side dead time when the input logic goes from 0 to 1.

  • tpHLis high-side propagation delay when the input logic goes from 1 to 0.

  • tdHLis low-side dead time when the input logic goes from 1 to 0.

Faults

You can insert a fault into one or both of the outputs at a specified simulation time. The fault options are:

  • 失败在lo输入固定gic 0

  • 不能输入固定的逻辑1

  • Fail high side off

  • Fail high side on

  • Fail low side off

  • Fail low side on

  • Fail high and low sides off

  • Fail high and low sides on

Ports

Input

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Input physical signal that specifies the input control value.

Dependencies

To enable this port, setModeling optiontoPS input.

Conserving

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Electrical conserving port associated with the pulse-width modulated signal.

Dependencies

To enable this port, setModeling optiontoElectrical input ports.

Electrical conserving port associated with the floating zero volt reference.

Dependencies

To enable this port, setModeling optiontoElectrical input ports.

Electrical conserving port associated with the gate on the high side of the half bridge. Connect this port to the gate of a MOSFET or IGBT block.

Electrical conserving port associated with the source or emitter on the high side of the half bridge. Connect this port to the source of a MOSFET block or the emitter of an IGBT block.

Electrical conserving port associated with the gate on the low side of the half bridge. Connect this port to the gate of a MOSFET or IGBT block.

Electrical conserving port associated with the source or emitter on the low side of the half bridge. Connect this port to the source of a MOSFET block or the emitter of an IGBT block.

Parameters

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Whether to model physical signal or electrical input ports.

Input Logic

Value of the input signal corresponding to the logic 1 level.

Dependencies

To enable this port, setModeling optiontoPS input.

Value of the input signal corresponding to the logic 0 level.

Dependencies

To enable this port, setModeling optiontoPS input.

Value of the input voltage corresponding to the logic 1 level.

Dependencies

To enable this port, setModeling optiontoElectrical input ports.

Value of the input voltage corresponding to the logic 0 level.

Dependencies

To enable this port, setModeling optiontoElectrical input ports.

Outputs

Demanded output voltage when the driver is in on state.

Demanded output voltage when the driver is in off state.

Timing

Low-side propagation delay when the input logic goes from 0 to 1.

High-side dead time when the input logic goes from 0 to 1.

High-side propagation delay when the input logic goes from 1 to 0.

Low-side dead time when the input logic goes from 1 to 0.

Dynamics

Select the type of driver parameterization:

  • Output impedance— Specify on-state and off-state gate drive resistances.

  • Rise and fall times— Specify rise time, fall time, and load capacitance.

Demanded output voltage when the driver is in on state.

Dependencies

Enabled when theParameterizationparameter is set toOutput impedance.

Demanded output voltage when the driver is in off state.

Dependencies

Enabled when theParameterizationparameter is set toOutput impedance.

Driver rise time from 10% to 90%.

Dependencies

Enabled when theParameterizationparameter is set toRise and fall times.

Driver fall time from 90% to 10%.

Dependencies

Enabled when theParameterizationparameter is set toRise and fall times.

Driver load capacitance.

Dependencies

Enabled when theParameterizationparameter is set toRise and fall times.

Faults

SelectYesto enable faults modeling. The associated parameters in theFaultssection become visible to let you specify time to fail and the failure mode.

Set the simulation time at which you want the block to enter the faulted state.

Dependencies

Enabled when theEnable faultsparameter is set toYes.

Select the driver state after the failure.

Dependencies

Enabled when theEnable faultsparameter is set toYes.

Model Examples

Buck Converter

Buck Converter

Model a switching power supply that converts a 30V DC supply into a regulated 15V DC supply. The model can be used to both size the inductance L and smoothing capacitor C, as well as to design the feedback controller. By selecting between continuous and discrete controllers, the impact of discretization can be explored.
Open Model

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2017b

See Also

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