Documentation

Deployment and Verification

创建包含用户编程和d比特流ownload it to Xilinx®Zynq®Platform

HDL Coder™ can generate an IP core, integrate it into your EDK project, and program the Zynq hardware. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM®processor.

Topics

Default System Reference Design

Learn about the default system reference design and using the reference design.

Default System with AXI4-Stream Interface Reference Design

Learn about how to use the default system with AXI4-Stream Interface reference design and its requirements.

Default Video System Reference Design

Learn about the default video system reference design and its requirements.

Default System with External DDR3 Memory Access Reference Design

Learn about the default system with external DDR3 memory access reference design and its requirements.

Featured Examples

Running an Audio Filter on Live Audio Input Using a Zynq Board

Running an Audio Filter on Live Audio Input Using a Zynq Board

Please click following link to view the HDL Coder example Running an audio filter on live audio input using a Zynq board.
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Debug a Zynq Design Using HDL Coder and Embedded Coder

Debug a Zynq Design Using HDL Coder and Embedded Coder

Please click following link to view the HDL Coder example Debug a Zynq Design Using HDL Coder and Embedded Coder.
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Debug IP Core Using FPGA Data Capture

Debug IP Core Using FPGA Data Capture

This example shows how to debug HDL Coder generated IP Core using HDL Verifier's FPGA Data Capture feature.
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HDL Coder Support Package for Xilinx Zynq Platform Documentation
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