FPGA-in-the-Loop Simulation

Verification with FPGA hardware

运行一个仿真金宝app软件^®or MATLAB^®simulation that is synchronized with an HDL design running on a Xilinx^®FPGA board.

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FPGA-in-the-Loop Simulation(HDL Verifier)

FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.

FPGA-in-the-Loop Simulation Workflows(HDL Verifier)

Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.

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Verification with FPGA Hardware(HDL Verifier)

Featured Examples

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

建立一个fpga在-the-Loop (FIL) application using HDL Verifier™. The application uses Simulink® and an FPGA development board to verify the HDL implementation of a proportional-integral-derivative (PID) controller. In this example, Simulink generates the desired position of a motor and simulates the motor controlled by this PID controller.

Open Model

FPGA-in-the-Loop Simulation

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Related Information

Featured Examples

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop

HDL Verifier Support Package for Xilinx FPGA Boards Documentation

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