Deployment

Create bitstream containing user programming and download it to the FPGA processor chip

To program the FPGA and run your algorithm on the hardware, HDL Coder™ can generate an IP core, and deploy it to the Intel^®FPGA boards. You can also program the FPGA board by using the FPGA Turnkey workflow, which generates HDL code for your algorithm and the FPGA top level wrapper and then deploys your design to the board.

Topics

IP Core Generation

IP Core Generation Workflow for Intel FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.
Default System Reference Design
设计一个学习系统默认引用d using the reference design.

FPGA Turnkey

Program Standalone Altera FPGA Development Board from MATLAB
FPGA Turnkey workflow for deployment to standalone FPGA hardware.
Program Standalone Altera FPGA Development Board from Simulink
This example shows how to target an Altera^®FPGA development board for synthesis using the FPGA Turnkey workflow.

Featured Examples

Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers by enabling the reference design parameter optionInsert JTAG AXI Manager. You can then access DUT registers from MATLAB® directly. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.

IP Core Generation of an I2C Controller IP to Configure the Audio Codec Chip

Illustrates how to model an I2C controller using an I2C Master controller modeled using Stateflow™ blocks for configuring the audio codec chip.

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