流radix 2^2Architecture

Modern ADCs are capable of sampling signals at sample rates up to several gigasamples per second. However, clock speeds for the fastest FPGA fall short of this sample rate. FPGAs typically run at hundreds of MHz. One way to perform GSPS processing on an FPGA is to process multiple samples at the same time at a much lower clock rate. Many modern FPGAs support the JESD204B standard interface which accepts scalar input at a GHz clock rate, and produces a vector of samples at a lower clock rate. Therefore, modern signal processing requires vector processing.

The流radix 2^2architecture is designed to support high-throughput applications. This example model uses an input vector size of 8 and theArchitectureparameter of the FFT block is set to流radix 2^2. For a timing diagram, supported features, and FPGA resource usage, seeFFT.

modelname ='FFTHDLOptimizedExample_Streaming'; open_system(modelname);

The InitFcn callback function (Model Properties > Callbacks > InitFcn) sets parameters for the model. In this example, the parameters control the size of the FFT and the input data characteristics.

FFTLength = 512;

输入数据是两个正弦波，200 kHz和250 kHz，每个都以1*2e6 Hz采样。The input vector size is 8 samples.

frameize = 8;FS = 1*2E6;

证明使用有效的control signal for noncontinuous input data, this example applies valid input every other cycle.

有效pattern = [1,0];

Open the Spectrum Viewer and run the example model.

open_system（'ffthdloptimizedexample_streaming/spectrum查看器/电源频谱查看器'); set_param(modelname,'SimulationCommand','开始')

Use the Logic Analyzer to view the input and output signals of theFFT流子系统。波形表明，输入有效信号每个第二个周期都高，并且在块返回第一个有效的输出样本之前存在一些延迟。块蒙版将显示从第一个有效输入到第一个有效输出的延迟，假设输入有效示例中没有差距。在这种情况下，由于输入流中的间隙，实际延迟比显示的延迟更长。该块在有效示例中返回没有空白的输出数据。

爆发radix 2（最小资源）体系结构

Use the爆发radix 2FPGA资源有限的应用程序的体系结构，尤其是在FFT长度较大时。该体系结构仅使用一种复杂的蝴蝶来计算FFT。在这个模型中，Architectureparameter of the FFT block is set to爆发radix 2.

When you select this architecture, the block has an output control signal,准备好，这表明该块何时可以接受新的输入数据。块设置准备好信号为1（真的) when it can accept data and starts processing once the whole FFT frame is saved into the memory. While processing, the block cannot accept data, so the block sets the准备好信号为0（false). You must apply data only when the准备好signal is 1. The block ignores any data applied while the准备好signal is 0.

有关定时图，支持功能和FPGA资源使用情况，金宝app请参见FFT.

modelname ='ffthdloptimizedexample_burst'; open_system(modelname);

The InitFcn callback function (Model Properties > Callbacks > InitFcn) sets parameters for the model. In this example, the parameters control the size of the FFT and the input data characteristics.

FFTLength = 512;

输入数据是两个正弦波，200 kHz和250 kHz，每个都以1*2e6 Hz采样。数据每个周期都是有效的。

FS = 1*2E6;有效pattern = 1;

Open the Spectrum Viewer and run the example model.

open_system（'FFTHDLOptimizedExample_Burst/Spectrum Viewer/Power Spectrum viewer'); set_param(modelname,'SimulationCommand','开始')

Use the Logic Analyzer to view the input and output signals of theFFT爆发子系统。The waveform shows that the input data arrives in bursts of valid samples, and that there is some latency before the block returns the valid output samples. The latency in the waveform matches the latency displayed on the block mask. The block also returns an output准备好signal that indicates when it has room to start accepting the next burst of input data. To ensure that the next burst of input data is not applied before the block sets the准备好信号为1（真的), the model uses the ready signal as an enable signal for the input data generation.

Generate HDL Code and Test Bench

您必须拥有HDL编码器产品来为此示例生成HDL代码。您的模型必须具有针对HDL代码生成的子系统。

选择一种模型来生成HDL代码并为FFT子系统进行测试工作台。

systemname ='FFTHDLOptimizedExample_Burst/FFT Burst';

或者

systemname ='ffthdloptimizedexample_streaming/fft流';

然后，使用此命令为该子系统生成HDL代码。生成的代码可用于任何FPGA或ASIC目标。

makehdl（systemName）;

使用此命令生成一个测试工作台，将HDL模拟的结果与Simulink模拟行为进行比较。金宝app

makehdltb(systemname);