Jack Erickson, MathWorks
Prototyping a design on an FPGA enables high-speed processing of real-world input, but debugging when problems occur is extremely difficult due to the lack of visibility of internal signals. FPGA Data Capture in HDL Verifier™ enables you to define signals in the FPGA to probe, and automatically generates the components needed to connect your FPGA board to MATLAB®or Simulink®to analyze signals. See this capability in action, together with Logic Analyzer, using an audio design example.
Recorded: 8 Mar 2017
Featured Product
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select:.
Selectweb siteYou can also select a web site from the following list:
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.