FPGA设计与MATLAB

This video series will show you how to adapt your signal processing algorithms for FPGA design. Using a pulse detection algorithm as an example, this tutorial-style series starts with the basics of what is needed for successful FPGA design, and incrementally adapts the algorithm to ready it for automatic implementation.

4:19

Part 1: Why Use MATLAB and SimulinkLearn how to adapt a signal processing application for FPGA design using MATLAB and Simulink.

4:42

Part 2: Modeling Hardware in SimulinkUse Simulink and HDL-ready blocks to design and visualize the high-level architecture of your FPGA design.

4:48

Part 3: Architecting Efficient HardwareLearn how to balance speed and area optimization of hardware micro-architecture for RTL generation.

5:41

Part 4: Converting to Fixed PointQuantize data types to reduce hardware resources in the FPGA design while maintaining sufficient precision.

5:23

Part 5: Generating and Synthesizing RTLUse the HDL Workflow Advisor to prepare, generate, synthesize, and analyze the RTL.

Related Resources

Get HDL Coder Self-Guided Tutorial
Request HDL Coder Trial