“ DesignFocus”

Closed-loop performance objective to favor in the design. For a given target phase margin,pidtunechooses a controller design that balances the two measures of performance, reference tracking and disturbance rejection. When you change theDesignFocusoption, the tuning algorithm attempts to adjust the PID gains to favor either reference tracking or disturbance rejection while achieving the same target phase margin. In the control architecture assumed bypidtune, shown in the following diagram, reference tracking is the response atyto signals atr, and disturbance rejection is the suppression atyof signals atd。

TheDesignFocus选项可以采用以下值：

系统中的可调参数越多，PID算法就越有可能在不牺牲鲁棒性的情况下实现所需的设计焦点。例如，与P或PI控制器相比，设置设计焦点对PID控制器更有效。在所有情况下，您可以如何微调系统的性能很大程度上取决于植物的特性。

For an example illustrating the effect of this option, seeTune PID Controller to Favor Reference Tracking or Disturbance Rejection (Command Line)。

Default:'balanced'

'numunstablepoles'

Number of unstable poles in the plant. When your plant is afrdmodel or a state-space model with internal delays, you must specify the number of open-loop unstable poles (if any). Incorrect values might result in PID controllers that fail to stabilize the real plant. (pidtuneignores this option for other model types.)

Unstable poles are poles located at:

A pure integrator in the plant (s= 0) or (|z| > 1) does not count as an unstable pole forNumUnstablePoles。If your plant is afrdmodel of a plant with a pure integrator, for best results, ensure that your frequency response data covers a low enough frequency to capture the integrator slope.

Default:0