包裹:DLHDL
配置自定义深度学习处理器
使用dlhdl.processorconfig
配置自定义处理器的类,然后将其传递到dlhdl.buildprocessor
生成自定义深度学习处理器的课程。
这dlhdl.processorconfig
类创建一个自定义处理器配置对象,您可以用来指定处理器参数。然后,处理器参数由dlhdl.buildprocessor
为您的自定义深度学习处理器构建和生成代码的课程。
dlhdl.processorconfig(名称,值)
创建一个自定义处理器配置对象,其中一个或多个名称值参数指定的其他选项。
processorconfig
目的创建自定义处理器配置。保存processorconfig
反对HPC
。
hpc = dlhdl.processorconfig
结果是:
hPC = Processing Module "conv" ConvThreadNumber: 16 InputMemorySize: [227 227 3] OutputMemorySize: [227 227 3] FeatureSizeLimit: 2048 KernelDataType: 'single' Processing Module "fc" FCThreadNumber: 4 InputMemorySize: 25088 OutputMemorySize: 4096 KernelDataType: 'single' Processing Module "adder" InputMemorySize: 40 OutputMemorySize: 40 KernelDataType: 'single' System Level Properties TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit' TargetFrequency: 200 SynthesisTool: 'Xilinx Vivado' ReferenceDesign: 'AXI-Stream DDR Memory Access :3-axim'nesthesistoolChipFaMily:'zynq ultrascale+'nesthesistooldeviceName:'xczu9eg-ffvb1156-2-e'synthesistoolpackagagagagagagagagagagagagagagagagagagagename:'synthesistoolspeedvalue:'''''''''''''''''
processorconfig
目的修改目标平台
,,,,合成学
, 和目标频率
属性HPC
。
hpc.targetplatform ='Xilinx Zynq ZC706评估套件';>> hpc.synthesistool ='xilinx vivado';>> hpc.targetfrequency = 180;HPC
结果是:
hPC = Processing Module "conv" ConvThreadNumber: 16 InputMemorySize: [227 227 3] OutputMemorySize: [227 227 3] FeatureSizeLimit: 2048 KernelDataType: 'single' Processing Module "fc" FCThreadNumber: 4 InputMemorySize: 25088 OutputMemorySize: 4096 KernelDataType: 'single' Processing Module "adder" InputMemorySize: 40 OutputMemorySize: 40 KernelDataType: 'single' System Level Properties TargetPlatform: 'Xilinx Zynq ZC706 evaluation kit' TargetFrequency: 180 SynthesisTool: 'Xilinx Vivado' ReferenceDesign: 'AXI-Stream DDR Memory Access : 3-Axim'SynthesistoolChipFamily:'Zynq Ultrascale+'SynthesistooldeviceName:'XCZU9EG-FFVB1156-2-E'SynthesistoolPackagagagagagagagagagagagagagagagagagagagename:'synthesistoolSpeedValue:'''''''''''
processorconfig
对象的zcu102_single
比特斯流检索processorconfig
对象zcu102_single
bitstream并将对象存储在HPC
。
hpc = dlhdl.processorconfig('bitstream',,,,'zcu102_single')
结果是:
hPC = Processing Module "conv" ConvThreadNumber: 16 InputMemorySize: [227 227 3] OutputMemorySize: [227 227 3] FeatureSizeLimit: 2048 KernelDataType: 'single' Processing Module "fc" FCThreadNumber: 4 InputMemorySize: 25088 OutputMemorySize: 4096 KernelDataType: 'single' Processing Module "adder" InputMemorySize: 40 OutputMemorySize: 40 KernelDataType: 'single' System Level Properties TargetPlatform: 'Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit' TargetFrequency: 220 SynthesisTool: 'Xilinx Vivado' ReferenceDesign: 'AXI-Stream DDR Memory Access :3-axim'nesthesistoolChipFaMily:'zynq ultrascale+'nesthesistooldeviceName:'xczu9eg-ffvb1156-2-e'synthesistoolpackagagagagagagagagagagagagagagagagagagagename:'synthesistoolspeedvalue:'''''''''''''''''