Downsample

Resample input at lower rate by deleting samples

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library:
DSP System Toolbox / Signal Operations
DSP System Toolbox HDL Support / Signal Operations

Description

The Downsample block decreases the sampling rate of the input by deleting samples. When the block performs frame-based processing, it resamples the data in each column of theM_i-by-Ninput matrix independently. When the block performs sample-based processing, it treats each element of the input as a separate channel and resamples each channel of the input array across time. The resample rate isKtimes lower than the input sample rate, whereKis the value of theDownsample factorparameter. The Downsample block resamples the input by discardingK–1 consecutive samples following each sample that is output.

This block supports triggered subsystems when you set theRate optionsparameter toEnforce single-rate processing.

Ports

Input

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`Port_1`— Data input
column vector | matrix |N-D array

Data input whose sampling rate is to be decreased by the block, specified as a column vector or a matrix.

When you set theInput processingparameter toElements as channels (sample based),input can be anN-D array.

Output

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`Port_1`— Downsampled output
column vector | matrix

Downsampled output with a sampling rate that is 1/Ktimes the input sampling rate, returned as a column vector or a matrix.

Parameters

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`Downsample factor, K`— Downsampling factor
`2`(default) | positive integer

The integer factor,K, by which to decrease the input sample rate.

`Sample offset (0 to K-1)`— Sample offset
`0`(default) | integer

TheSample offsetparameter delays the output samples by an integer number of sample periods,D, where 0 ≤D≤ (K–1), so that any of theKpossible output phases can be selected. For example, when you downsample the sequence 1, 2, 3, ... by a factor of 4, you can select from four phases.

Input Sequence	Sample Offset, D	Output Sequence (K= 4)
`1,2,3,...`	0	`1,5,9,13,17,21,25,29,...`
`1,2,3,...`	1	`0,2,6,10,14,18,22,26,...`
`1,2,3,...`	2	`0,3,7,11,15,19,23,27,...`
`1,2,3,...`	3	`0、4、8、12、16、20、24、28日……`

The initial zero in each of the latter three output sequences in the table is a result of the default zeroInitial conditionsparameter setting for this example. Seelatencyfor more information on theInitial conditionsparameter.

`Input processing`— Method to process input
`Columns as channels (frame based)`(default) |`Elements as channels (sample based)`

Specify the method for input processing:

Columns as channels (frame based)–– When you set theInput processingparameter toColumns as channels (frame based),block treats each of theNinput columns as an individual channel containingM_isequential time samples. The block downsamples each channel independently by discardingK–1 rows of the input matrix following each row that it outputs.
For more information, seeWhat Is Frame-Based Processing?.
Elements as channels (sample based)–– When you set theInput processingparameter toElements as channels (sample based),input can be anN-D array. TheDownsampleblock treats each element of the input as a separate channel, and resamples each channel of the input over time. The block downsamples the input array by discardingK–1 samples following each sample that it passes through to the output. The input and output sizes of the Downsample block are identical.
For more information, seeWhat Is Sample-Based Processing?.

`Rate options`— Enforce single-rate or allow multirate processing
`Enforce single-rate processing`(default) |`Allow multirate processing`

Specify the method by which the block adjusts the rate at the output to accommodate the reduced number of samples. . You can select one of the following options. The behavior of these options depends on whether theInput processingparameter is set toElements as channels (sample based)(sample-based processing mode) orColumns as channels (frame based)(frame-based processing mode).

Elements as channels (sample based)
- Enforce single-rate processing
  The block forces the output sample rate to match the input sample rate (T_so=T_si) by repeating everyKth input sampleK次输出。在这种模式下,的行为the block is similar to the operation of a Sample and Hold block with a repeating trigger event of periodKT_si.
- Allow multirate processing
  The sample period of the output isKtimes longer than the input sample period (T_so=KT_si).
Columns as channels (frame based)
- Enforce single rate processing
  The block generates the output at the slower (downsampled) rate using a proportionally smaller framesizethan the input. For downsampling by a factor ofK,output frame size isKtimes smaller than the input frame size (M_o=M_i/K), but the input and output frame rates are equal.
  Theex_downsample_ref2model shows a single-channel input with a frame size of 64 being downsampled by a factor of 4 to a frame size of 16. The input and output frame rates are identical.
- Allow multirate processing
  The block generates the output at the slower (downsampled) rate by using a proportionally longer frameperiodat the output port than at the input port. For downsampling by a factor ofK,output frame period isKtimes longer than the input frame period (T_fo=KT_fi), but the input and output frame sizes are equal.
  Theex_downsample_ref1model shows a single-channel input with a frame period of 1 second being downsampled by a factor of 4 to a frame period of 4 seconds. The input and output frame sizes are identical.

`Initial conditions`— Initial value
`0`(default) | real scalar | array

The initial block value for cases of nonzero latency. You can specify a scalar or an array of the same size as the input.

Dependencies

This parameter appears only when you set theRate optionsparameter toAllow multirate processing.

Model Examples

Acoustic Noise Cancellation (LMS)

Use the Least Mean Square (LMS) algorithm to subtract noise from an input signal. The LMS adaptive filter uses the reference signal on theInputport and the desired signal on theDesiredport to automatically match the filter response. As it converges to the correct filter model, the filtered noise is subtracted and the error signal should contain only the original signal.

Downsample a Signal

Downsampling operation on a signal with one-frame latency.

Block Characteristics

Data Types	`Boolean`\|`double`\|`fixed point`\|`integer`\|`single`
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

More About

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latency

latency is the delay, measured in samples or frames, between the input and the output of the block.

The Downsample block haszero-tasking latencyin the following cases:

TheDownsample factorparameter,K, is1.
TheInput processingparameter is set toColumns as channels (frame based), and theRate optionsparameter is set toEnforce single-rate processing.
TheInput processingparameter is set toColumns as channels (frame based),Rate optionsparameter is set toAllow multirate processing,Sample offsetparameter,D, is set to0, and the input frame size is equal to 1.
TheInput processingparameter is set toElements as channels (sample based), and theSample offsetparameter,D, is0.

Zero-tasking latency means that the block propagates input sampleD+1 (received att= 0) as the first output sample, followed by input sampleD+1+K, input sampleD+1+2K, and so on. When there is zero-tasking latency, the block ignores the value of theInitial conditionsparameter.

In all other cases, the latency is nonzero:

When theInput processingparameter is set toElements as channels (sample based),latency is one sample.
When theInput processingparameter is set toColumns as channels (frame based)and the input frame size is greater than one, the latency is one frame.

In all cases ofone-sample latency,initial condition for each channel appears as the first output sample. Input sampleD+1 appears as the second output sample for each channel, followed by input sampleD+1+K, input sampleD+1+2K, and so on. TheInitial conditionsparameter can be an array of the same size as the input or a scalar to be applied to all signal channels.

In all cases ofone-frame latency,M_irows of the initial condition matrix appear in sequence as the firstM_ioutput rows. Input sampleD+1 (rowD+1 of the input matrix) appears in the output as sampleM_i+1, followed by input sampleD+1+K, input sampleD+1+2K, and so on. TheInitial conditionsvalue can be anM_i-by-Nmatrix containing one value for each channel or a scalar to be repeated across all elements of theM_i-by-Nmatrix.

Note

For more information on latency and the Simulink^®tasking modes, seeExcess Algorithmic Delay (Tasking Latency)andTime-Based Scheduling and Code Generation(Simulink Coder).

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Generated code relies onmemcpyormemsetfunctions (string.h) under certain conditions.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

Best Practices

It is good practice to follow the Downsample block with a unit delay. Doing so prevents the code generator from inserting an extra bypass register in the HDL code.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	寄存器的数量在mov的输出ing existing delays within your design. Distributed pipelining does not redistribute these registers. The default is`0`. For more details, seeConstrainedOutputPipeline(HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeInputPipeline(HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is`0`. For more details, seeOutputPipeline(HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Restrictions

Input processingset toColumns as channels (frame based)is not supported.
ForInput processingset toElements as channels (sample based), selectAllow multirate processing. With this setting, ifSample offsetis set to 0,Initial conditionshas no effect on generated code.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

DSP System Toolbox Documentation

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Downsample

Description

Ports

Input

`Port_1`— Data input
column vector | matrix |N-D array

Output

`Port_1`— Downsampled output
column vector | matrix

Parameters

`Downsample factor, K`— Downsampling factor
`2`(default) | positive integer

`Sample offset (0 to K-1)`— Sample offset
`0`(default) | integer

`Input processing`— Method to process input
`Columns as channels (frame based)`(default) |`Elements as channels (sample based)`

`Rate options`— Enforce single-rate or allow multirate processing
`Enforce single-rate processing`(default) |`Allow multirate processing`

`Initial conditions`— Initial value
`0`(default) | real scalar | array

Dependencies

Model Examples

Acoustic Noise Cancellation (LMS)

Downsample a Signal

Block Characteristics

More About

latency

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Blocks

Topics

DSP System Toolbox Documentation

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Try MATLAB, Simulink, and Other Products

Downsample

Description

Ports

Input

Port_1— Data inputcolumn vector | matrix |N-D array

Output

Port_1— Downsampled outputcolumn vector | matrix

Parameters

Downsample factor, K— Downsampling factor2(default) | positive integer

Sample offset (0 to K-1)— Sample offset0(default) | integer

Input processing— Method to process inputColumns as channels (frame based)(default) |Elements as channels (sample based)

Rate options— Enforce single-rate or allow multirate processingEnforce single-rate processing(default) |Allow multirate processing

Initial conditions— Initial value0(default) | real scalar | array

Dependencies

Model Examples

Acoustic Noise Cancellation (LMS)

Downsample a Signal

Block Characteristics

More About

latency

Extended Capabilities

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Code GenerationGenerate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point ConversionDesign and simulate fixed-point systems using Fixed-Point Designer™.

See Also

Blocks

Topics

DSP System Toolbox Documentation

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Try MATLAB, Simulink, and Other Products

`Port_1`— Data input
column vector | matrix |N-D array

`Port_1`— Downsampled output
column vector | matrix

`Downsample factor, K`— Downsampling factor
`2`(default) | positive integer

`Sample offset (0 to K-1)`— Sample offset
`0`(default) | integer

`Input processing`— Method to process input
`Columns as channels (frame based)`(default) |`Elements as channels (sample based)`

`Rate options`— Enforce single-rate or allow multirate processing
`Enforce single-rate processing`(default) |`Allow multirate processing`

`Initial conditions`— Initial value
`0`(default) | real scalar | array

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.