HDL Verifier™ automatically generates test benches for Verilog^®and VHDL^®design verification. You can use MATLAB^®or Simulink^®to directly stimulate your design and then analyze its response using HDL cosimulation or FPGA-in-the-loop with Xilinx^®and Altera^®FPGA板。这种方法消除了需要author standalone Verilog or VHDL test benches.

HDL Verifier also generates components that reuse MATLAB and Simulink models natively in simulators from Cadence^®, Mentor Graphics^®, and Synopsys^®. These components can be used as verification checker models or as stimuli in more complex test-bench environments such as those that use the Universal Verification Methodology (UVM).