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Hardware-Software Co-Design Overview

The hardware-software (HW/SW) co-design feature in this support package enables you to prototype an SDR algorithm on the USRP™ E3xx embedded series radio hardware.The implementation is partitioned between the ARM®processor and the FPGA fabric of the underlying Zynq®system on chip (SoC). In general, you use the ARM processor to implement slower-rate control functionality, and you use the FPGA fabric to implement high-rate signal processing. When the algorithm is deployed, you can control and tune parameters on the HDL logic.

In this diagram, the generated Transmit/Receive software blocks are placed in the ARM section,ARM (PS), and the Transmit/Receive user logic blocks are placed in the FPGA fabric section,织物(PL).

Software Requirements for HW/SW Co-Design

Note

The HW/SW co-design workflow is available in Simulink®only.

The HW/SW co-design workflow in the Communications Toolbox™ Support Package for USRP Embedded Series Radio requires additional software and third-party tools.

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  • To target the FPGA fabric on the device:HDL Coder™ Support Package for Xilinx®Zynq Platform(requires HDL Coder)

  • To target the ARM processor on the device:Embedded Coder®Support Package for Xilinx Zynq Platform(requires Embedded Coder,Simulink Coder™, andEmbedded Coder Support Package for ARM Cortex®-A Processors)

Third-Party Tools

  • Xilinx Vivado®development tools, version 2019.1

Limitations

In single-channel mode, transmit and receive data frames must contain an even number of samples.

Default FPGA Resource Utilization onUSRPE310

Get Started

To get started with the HW/SW co-design workflow in this support package:

  1. Install the required additional software and third-party tools. SeeInstallation for Hardware-Software Co-Design.

  2. Follow the guidedHardware-Software Co-Design Workflow. To prototype SDR algorithms on the FPGA fabric only, follow theFPGA Targeting Workflowinstead.

To learn more about the HW/SW co-design workflow on SoC platforms, seeHardware-Software Co-Design Workflow for SoC Platforms(HDL Coder).

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