HDL Coder Support Package for Xilinx FPGA Boards

Generate HDL code forXilinxdevelopment boards

HDL Coder™ Support Package for Xilinx^®FPGA Boardsenables IP core generation and FPGA turnkey workflows to program supported Xilinx FPGAs. The IP core generation and FPGA turnkey workflows help you map your algorithm I/O to onboard interfaces, generate HDL code, and synthesize the generated code. HDL Coder also provides integration with Xilinx Vivado^®or Xilinx ISE to synthesize the generated code into a bitstream that you can directly download on to Xilinx FPGA development boards.

Setup and Configuration

Setup and install the support package for use with supported third-party tools and hardware

Hardware-Software Co-Design Basics

Learn about the hardware-software co-design workflow and how to use the Workflow Advisor to run the algorithm on an FPGA board

Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board

Custom Board and Reference Design

Define and register custom reference design or custom board for Xilinx FPGA

Deployment

Create bitstream containing user programming and download it to the FPGA hardware