函数最高级的_programFPGA %加载FPGA filProgramFPGA比特流(Xilinx, / dir / mybitstream。一点',1);结束

classdef fft8_fil < hdlverifier。FILSimulation% fft8_fil is a filWizard generated class used for FPGA-In-the-Loop % simulation with the 'fft8' DUT. % fft8_fil connects MATLAB with a FPGA and cosimulate with it by % writing inputs in the FPGA and reading outputs from the FPGA. % % MYFIL = fft8_fil % % FIL syntax: % % [out1, out2, ...] = MYFIL(in1, in2, ...) connect to the FPGA, % write in1, in2, ... to the FPGA and read out1, out2, ... from % the FPGA % % fft8_fil methods: % % release - Allow property value and input characteristics changes, and % release connection to FPGA board % clone - Create fft8_fil object with same property values % isLocked - Locked status (logical) % programFPGA - Load the programming file in the FPGA % % fft8_fil properties: % % DUTName - DUT top level name % InputSignals - Input paths in the HDL code % InputBitWidths - Width in bit of the inputs % OutputSignals - Output paths in the HDL code % OutputBitWidths - Width in bit of the outputs % OutputDataTypes - Data type of the outputs % OutputSigned - Sign of the outputs % OutputFractionLengths - Fraction lengths of the outputs % OutputDownsampling - Downsampling factor and phase of the outputs % OverclockingFactor - Overclocking factor of the hardware % SourceFrameSize - Frame size of the source (only for HDL source block) % Connection - Parameters for the connection with the board % FPGAVendor - Name of the FPGA chip vendor % FPGABoard - Name of the FPGA board % FPGAProgrammingFile - Path of the Programming file for the FPGA % ScanChainPosition - Position of the FPGA in the JTAG scan chain % % File Name: fft8_fil.m % Created: 26-Apr-2012 18:18:06 % % Generated by FIL Wizard properties (Nontunable) DUTName = 'fft8'; end methods function obj = fft8_fil %THE FOLLOWING PROTECTED PROPERTIES ARE SPECIFIC TO THE HW DUT %AND MUST NOT BE EDITED (RERUN THE FIL WIZARD TO CHANGE THEM) obj.InputSignals = char('Xin_re','Xin_im'); obj.InputBitWidths = [10,10]; obj.OutputSignals = char('Xout_re','Xout_im'); obj.OutputBitWidths = [13,13]; obj.Connection = char('UDP','192.168.0.2','00-0A-35-02-21-8A'); obj.FPGAVendor = 'Xilinx'; obj.FPGABoard = 'XUP Atlys Spartan-6 development board'; obj.ScanChainPosition = 1 ; %THE FOLLOWING PUBLIC PROPERTIES ARE RELATED TO THE SIMULATION %AND CAN BE EDITED WITHOUT RERUNING THE FIL WIZARD obj.OutputSigned = [true,true]; obj.OutputDataTypes = char('fixedpoint','fixedpoint'); obj.OutputFractionLengths = [9,9]; obj.OutputDownsampling = [1,0]; obj.OverclockingFactor = 1; obj.SourceFramieSize = 1; obj.FPGAProgrammingFile = 'S:\MATLAB\demo\fft8_fil\fft8_fil.bit'; end end end