Jack Erickson, Mathworks
Get an overview of HDL code generation and verification support in IEC Certification Kit for ISO 26262 and IEC 61508.
ISO 26262和IEC 61508的IEC认证套件已添加工作流程和工件文档,用于连接基于模型的设计,以实现功能安全到ASIC和FPGA实现。这包括来自TÜVSüd的证书,表明HDL编码器根据任何ASI的ISO 26262合格,并且还根据IEC 61508,IEC 62304,EN 50128和ISO 25119进行了适用性进行了测试。
This workflow includes:
The kit also provides templates for managing and documenting your workflow steps and artifacts. And if you require more extensive support in deploying this process, MathWorks offers anISO 26262 Process Deployment Advisory Service.
To learn more about the MathWorks ISO 26262 workflow, visitISO 26262 support in MATLAB and Simulink.
从2020版开始,高密度脂蛋白编码器一直问ualified for ISO 26262, including ASIL D. IEC Certification Kit for ISO 26262 and IEC 61508 from MathWorks has been updated with a full workflow for connecting Model-Based Design to FPGA and ASIC implementation.
该套件提供了工作流程和工件,以帮助您遵守 - 并证明您遵守这些功能安全标准。在“HDL部分”部分下,有来自TÜVSüd的证书,用于HDL编码器,以及他们的报告解释了用于资格认证的过程。
And this is more than just HDL Coder. The workflow document in the kit covers the process from requirements authoring, to architectural modeling, to modeling for implementation, then to HDL code generation, with verification and validation at each step.
As you can see, a big part of this workflow is first verifying that the model behaves according to requirements, which includes linking requirements to the models and tests, and making sure those requirements are fully covered in testing. Then as you get into implementation, verifying that each implementation stage produces a design whose functionality matches that of the previous stage.
This workflow also provides techniques to help ensure integrity through downstream FPGA or ASIC implementation. Before HDL code generation, use the Model Advisor to run task-specific checks. Here I will just run the ISO checks on our HDL tutorial design, which is a signal processing design that was not created with certification in mind, so it should identify plenty of issues.
没有错误,这很好,警告可以让您了解良好的做法,以防止在此级别的假设,导致下游问题。其中一些应该在设计中解决,其中一些涉及工具设置,例如增加检查诸如溢出等问题的严重程度。
And in terms of verifying the downstream implementation, HDL Verifier offers a number of ways to re-use your Model-Based Design work. What’s shown in this flow diagram is running your design on an FPGA running in-the-loop with your Simulink tests, and checking the results back-to-back against your model. You can also use HDL Verifier to generate SystemVerilog verification components for downstream simulation, including UVM. See the HDL Verifier product page to learn more.
This kit also shows how to integrate handwritten code into the process, and how to verify it together with your model using HDL Verifier.
最后,套件提供了一个模板,您可以使用项目来证明一致性。它列出了使用的条件,并提示您输入您流程中使用的相关信息。
MathWorks offers assistance and consulting to build your organizational proficiency with these functional safety workflows. And the kit itself provides some great resources to get you started.
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