金宝app^®is used widely for system-level simulation and early verification in FPGA and ASIC design projects. Many of these projects have blocks and subsystems that have already been written in VHDL^®or Verilog^®. HDL Verifier™ can import this handwritten or reused code into a cosimulation block that connects Simulink to an HDL simulator from Mentor^®or Cadence^®.

This video demonstrates the workflow for importing VHDL for a CORDIC function that will simulate in Mentor Questa^®connected to the test environment in Simulink. It also details how to specify data types and sample time mapping for accurate and efficient cosimulation.