Semtech Speeds Development of Digital Receiver FPGAs and ASICs

挑战

加速无线RF设备优化数字接收链的开发

Use MathWorks tools for Model-Based Design to generate production VHDL code for rapid FPGA and ASIC implementation

结果

  • 原型创造了50%更快
  • Verification time reduced from weeks to days
  • 优化,更好的性能设计

“写VHDL是乏味的,手写代码仍然需要验证。使用Sim金宝appulink和HDL编码器,一旦我们模拟了模型,我们就可以直接生成VHDL并原型FPGA。它节省了很多时间,而生成的代码包含一些我们没有想到的优化。“

Frantz Prianon,Semtech
Semtech SX1231 wireless transceiver.

无线RF接收器用于一系列应用,包括无线安全系统,工业监控,抄表和家庭自动化。在过去,半导体供应商主要使用模拟设计建立了这些接收器。如今,供应商正在转换到数字和混合信号设计,以降低功耗并简化与其他组件集成。

Engineers at Semtech are expanding their use of MathWorks tools for Model-Based Design to transition to a digital platform. For years, the engineers modeled and generated HDL code for filters with MATLAB®和过滤器设计HDL编码器。On their most recent project, they used Simulink®and HDL Coderto generate VHDL®对于整个设计。

“There is no advantage to writing VHDL by hand,” says Frantz Prianon, IC design engineer at Semtech. “With Simulink and HDL Coder, we have one model of the system. We simulate it, so we know it works. And we generate code from it, so we can use one model until the end of the project. This is an important capability, because we are sure that what we have implemented matches the design and that the design meets specifications.”

挑战

SEMTECH工程师需要开发用于频移键控(FSK)的数字接收器链和使用低IF架构的最小移位键控(MSK)解调。他们希望在项目的验证期间评估性能,功耗和布局区域的多种设计理念。为每个设计的替代方案编写VHDL将是耗时的,限制团队可以考虑的替代品的数量。

超出原型阶段,SEMTECH工程师希望改善其传统开发工作流程的生产代码。“在我们建模我们的系统以确保他们满足要求之后,我们曾经在VHDL中重新实现它们,并在新工具中重新运行模拟,”普兰森说。“我们总是有机会引入错误,我们永远无法确定模型对应于新的VHDL代码。”

Semtech MathWorks使用基于模型的设计工具n to rapidly explore and evaluate design ideas, generate production VHDL code, improve collaboration among engineering teams, and accelerate the development of the digital receiver chain for FSK and MSK demodulation.

在PriStudy阶段,SEMTECH工程师基于系统规范在SIMULINK中创建了一个浮点模型。金宝app它们使用来自通信工具箱的块为了模拟通道中的噪声并实现FSK和MSK解调。

使用信号处理工具箱和DSP系统工具箱,一名工程师设计和分析了级联集成器 - 梳子(CIC)和有限脉冲响应(FIR)数字滤波器,而另一台工程师正在研究Sigma-Delta模数转换器(ADC),锁相环(PLL)以及使用Simulink的完整系统的其他部分。金宝app

Once the separate parts of the digital receiver chain had been simulated, the engineers shared their Simulink models with each other to verify that their component designs would work together before system integration.

The engineers ran simulations to verify the design and used the Error Rate Calculation block from Communications Toolbox to compute the bit error rate.

With Fixed-Point Designer, they converted the design from floating point to a fixed-point representation, which they used to conduct bit-true simulations.

SEMTECH工程师使用HDL编码器从完整接收链的SIMULINK模型生成VHDL。金宝app要验证VHDL,它们使用了HDL验证程序用它的模拟模拟设计金宝appMentor Graphics®Questa.®simulator

Semtech is currently working on the ASIC implementation of the receiver chain.

结果

  • 原型创造了50%更快。“当我们自己写VHDL时,它很容易需要两个月的时间来创造FPGA原型,”普兰森说。“通过Sim金宝appulink和HDL编码器,我们消除了每个块的繁琐手编码并在几周内创建原型。”

  • Verification time reduced from weeks to days。“在以前的项目上,我们将花费至少两周的写作长椅验证我们的VHDL,”普拉森召回。“使用HDL验证程序,我们可以运行Cosimulations,测试模型中的多个关键点,并验证VHDL,通常在不到一天内。”

  • 优化,更好的性能设计。基于模型的设计使EMTech能够缩短从需求到Tape-Out的开发时间约为33%。“我们使用了我们节省改善设计的时间,”普兰森说。“MathWorks工具使我们能够探索更多替代品和新功能,并最终提供更优化,更好的设计。”