通过集成电路（IC）实现的模数转换器（ADC）由于不完善的IC制造而容易出现错误。例如，晶体管，电阻器和电容器等不匹配的模拟成分可能导致信号失真，例如导致总谐波失真差（THD）。减少ADC错误的一种方法是使用较大的模拟组件来增强设计。这种方法改善了匹配，因此需要变形数字，但需要更多的区域和功率。第二种方法是增加校准电路，但这还需要额外的硅面积并增加成本和功耗 - 通常，人们需要知道要校准错误的确切原因。
At NXP Eindhoven, my colleague and I post-correct ADC errors using a neural network designed and trained with MATLAB®and Deep Learning Toolbox™. When implemented on an ASIC, the network requires just 15% of the area of the ADC while consuming roughly 16 times less power under normal operating conditions.
设计和培训神经网络
We generated training data in the lab by supplying a reference signal to 30 ADC samples (dies) and capturing the digital output. A further 10 samples were set aside for validating the network. Because ADC errors are affected by both temperature and voltage, we tested each sample at nine different voltage-temperature combinations, for a total of 360 measurements. We preprocessed our data using signal processing techniques and then used the measured digital output values of the ADC as inputs to the neural network. The network coefficients would be updated by comparing the corrected output signal with the original reference signal (Figure 1).
Figure 1. Neural network training setup.
因为我在项目开始时几乎没有神经网络的经验，所以我不确定网络需要多么复杂。我首先在MATLAB中创建基本的两层和三层网络，并改变每一层的神经元数。第一层和第二层中的神经元使用Sigmoid激活函数，并且输出层激活函数是线性的。使用的成本函数是最少的平均正方形（LMS）成本函数。
After training these early network configurations on our data set, I saw that I could improve their performance by incorporating voltage and temperature measurements as predictors. When I implemented this change, network performance improved significantly across a wide range of temperature and voltage conditions.
Evaluating IC Area and Power
Once I had a neural network that was effective at post-correcting ADC errors, I wanted to evaluate how much silicon area and power it would require. To do this, I generated a Simulink®model of the trained neural network from MATLAB. I then quantized all network coefficients using Fixed-Point Designer™ before generating VHDL®code from the network with HDL Coder™. My colleague verified the generated VHDL in Simulink via HDL Verifier™ cosimulation and then used Cadence®Genus to synthesize the design. He also used the Cadence environment to perform the physical implementation using 28 nm CMOS technology, generate power reports, and calculate the number of gates used and the area needed for these gates.
该分析的结果表明，在区域和功率方面，神经网络可以以相对较低的成本纠正ADC错误。一个将信噪比提高约17 dB的网络仅需4600多个大门，而硅面积为0.0084毫米2to implement. The ADC, which measures 0.06 mm2, is more than seven times larger than the network. When active, the network consumed about 15 µW of power, whereas the ADC consumed 233 µW.
Both the area and the power consumption estimates are considered acceptable for error-correcting circuits, but I’m confident that, with optimization, we could improve these numbers. The workflow used to implement the network in VHDL was very straightforward, despite my relative inexperience with machine learning. As a result, designing and implementing the neural network-based circuit took no longer than a traditional approach would have, even though I was new to the process.
Increasing Reusability and Portability
在短期内，我们计划探索几种验证神经网络进行ADC误差校正的途径。首先，我们希望更好地了解训练有素的网络如何执行误差校正，以便我们可以最大程度地降低生产中意外行为的风险。其次，我们想扩展我们的数据集。我们需要知道，如果我们使用一百万个样本而不是仅40个样本，我们所取得的结果是否会得出。最后，我们想衡量可重复使用的神经网络。我们预计，与传统设计相比，单个网络将能够更有效地补偿各种ADC的不同错误，因为网络可以容纳广泛的传输功能。但是，我们将需要进行进一步的测试以验证这一假设。
