Reference design name, specified as a character vector. In the HDL Workflow Advisor, this name appears in theReference designdrop-down list.

Example:“默认系统（Vivado 2015.4）”

Board associated with this reference design, specified as a character vector.

Example:“带PM3基板的Enclustra Mars ZX3”

One or more tool versions that work with this reference design, specified as a cell array of character vectors.

Example:{'2015.4'}

Example:{'13.7','14.0'}

One or more design constraint files, specified as a cell array of character vectors. This property is optional.

Example:{'MarsZX3_PM3.xdc'}

Example:{'mydesign.qsf'}

One or more relative paths to files or folders that the reference design requires, specified as a cell array of character vectors. This property is optional.

Examples of required files or folders:

Example:{'my_ip_core'}

Example:{fullfile('data', 'ps7_system_prj.xml')}

Example:{'ip'}

Example:{'ipcore'}

Example:{'pcores'}

Specify the device tree file name. For an example that shows how to use different device tree file names when mapping the DUT ports to different AXI4-Stream channels, seeDynamically Create Master Only or Slave Only or Both Master and Slave Reference Designs。

Example:'devicetree_axistream_iio.dtb'

Specify whether you want the parameterInsert JTAG MATLAB as AXI Master (HDL Verifier Required)to be displayed in the设定目标参考设计task of the HDL Workflow Advisor. By default, this property value is set to真的。The parameter is displayed in the设定目标参考设计任务。启用此属性后，要指定是否要代码生成器将JTAG MATLAB插入Axi Master IP，请使用JTAGMATLABasAXIMasterDefaultValueproperty. If you do not want the parameter to be displayed, set the property value tofalse。

This property is optional.

Example:'false'

Specify whether you want the code generator to insert the JTAG MATLAB as AXI Master IP. The values that you specify are the choices for theInsert JTAG MATLAB as AXI Master (HDL Verifier Required)drop-down in the设定目标参考设计task of the HDL Workflow Advisor. To specify insertion of the JTAG as AXI Master automatically, before you set this property to上，设置AddJTAGMATLABasAXIMasterParameterproperty to真的。

This property is optional.

Example:'on'

Specify the IP cache zip file to include in your project. When you run theIP Core Generationworkflow in the HDL Workflow Advisor, the code generator extracts this file in the创建项目任务。TheBuild FPGA Bitstreamtask reuses the IP cache, which accelerates reference design synthesis.

This property is optional.

Example:'ipcache.zip'

Specify whether you want the code generator to report timing failures in theBuild FPGA Bitstream任务是警告或错误。当您运行IP Core Generationworkflow in the HDL Workflow Advisor, by default, the code generator reports any timing failures as error. If you have implemented the custom logic to resolve timing failures, you can specify these failures to be reported as warning instead of error. To learn more, seeResolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows。

This property is optional.

Example:'hdlcoder.reporttiming.warning'

Specify if the reference design has an existing PS.

Example:'false'

Enable generation of device tree nodes for an HDL Coder generated IP core, and then insert the nodes into the device tree. To enable the generation of device tree nodes for the IP core,HasProcessingSystem必须设置为真的。

Do not enable this property if you do not need any additional device tree nodes to be inserted into the registered device tree for the generated IP core.

Example:'真的'

参考设计使用的董事会资源，作为带有字段的结构返回：